Step-by-Step Instructions
-- A Light Controlled by two Switches --
Concept to FPGA bit-streams & Download to Chip for real-time testing

Step 1a -- Designing Circuit using Verilog HDL & FPGA-based Boards - (2min & 39sec)

Step 1c -- Develop a Conceptual Design - (1min & 47sec)

Step 2 -- Writing the Verilog HDL Code - (0min & 44sec)

Step 3 -- Perform Simulation in Silos III - (5min)

Step 4 -- Develop a UCF file, create the bit-stream file in Xilinx, download and test in real-time - (14min & 38sec)

Step 5 -- (Alternative UCF file) -- Using a simplified UCF_Generator - (9min & 6sec)

Step 6 -- Use the simplified UCF file, examine the Xilinx floor-plan, timing reports, signals assigned to foot-prints etc... - (18min & 17sec)