EE-404

EE-404 Large Scale Digital Design

Ho - (Fall 2008)

Textbook &Software

Order online - http://direct.mbsbooks.com/capitol.htm (On the following three pages select: (1) "Resources" menu, top from right beside FAQ, (2) "E-Books" from More Resources column and (3) enter "1-4020-7089-6" in New & Used Books box and select "ISBN" on Keyword dropdown, click "Search" button.)

[ required ] The Verilog Hardware Description Language, 5th ed, by D. E. Thomas & P. R. Moorby, Springer, ISBN: 1-4020-7089-6
[ recommended ] Verilog HDL - A Guide to Digital Design and Synthesis, 2nd edition, by Samir Palnitkar, Prentice Hall,
ISBN 0-13-044911-3
[ recommended ] Modeling, Synthesis, and Rapid Prototyping with the VERILOG HDL, by Michael D. Ciletti, Prentice Hall, ISBN 0-13-977398-3
[ recommended ] Design Through Verilog HDL,by T.R. Padmanabhan & B.B.T. Sundari,IEEE press, Wiley-Interscience, ISBN 0-471-44148-1
[ required ] Xilinx ISE and ModelSIM
[ required ] SIMUCAD Inc, Silos 2001

Online References

[ recommended ] On-line Verilog HDL Quick Reference Guide
[ recommended ] Xilinx XST support for Verilog constructs
[ recommended ] Designer's Guide to Verilog
[ recommended ] Verilog Tutorial

Catalog Course Description

[ This Course ] EE-404 Large Scale Digital Design
[ Prerequisite ] EE-304 Digital Design I
[ 2007-2008 CAPITOL COLLEGE Catalog in Adobe PDF ]

WEEK TOPICS CHAPTERS & Appendices

1-2   Background and Course Overview
  S3BOARD, Nexys and Nexys2 Spartan 3, 3E boards
  Software Installation
  Introductory Xilinx Webpack, ModelSim and Silos 2001
     Xilinx ISE, ModelSIM & SILOS III
  Boards user manuals

3   Introductory Modeling with VERILOG HDL
  Hardware Encapsulation
  Structural Description
  Module, ports
  Testbench
  chap1

4-5   Logic Synthesis, Behavioral & Structural Modeling
  Combinational and FSM
  Tristates Coding Technique
  Latches, Flip-flops and Registers Modeling Techniques
  Counter Coding Technique

  chap2, 3

6   Current Processes
  Waits, Events and control statements
  Producer-Consumer Handshake
  Module Hierarchy
  Instantiation, Generate-endgenerate block
  chap4
  chap5

7-8   Logic Level Modeling
  Gates and Nets
  Primitives Logic Gates
  chap6

9 ********** Midterm Exam **********

10-12   User-Defined Primitives
  Combinational primitives
  Sequential primitives
  Level sensitive primitives
  Edge-sensitive primitives
  chap9

13-15   Switch Level Modeling
  Modeling MOS transistors
  Definition and using Strength levels
  chap10

16 ******* Final Exam ******

Laboratory Report

Laboratory Report of each project must adhere to the style guide practice at the college. Click the hypertext for detail.

Grades Policy on Incomplete Work

All works must be completed by the end of semester. In an exceptional case only will an incomplete will be issued, in such case we will follow the rules set forth in the current publication of the College Catalog on Incomplte Grades. Please click the hypertext for detail.

Grading

Course grade is based on the following distribution:

Midterm - 20%
Final - 30%
Lab Projects - 50%

Missed Exam

Due to unforeseen situation one may fail to take an exam. Ordinarilly make-up is held some later time. We believe this practice is unfair to those who took the test on time. So we will institute a no make-up policy. In this case, the final exam score will be raised to include the weight assign to the exam. As a reminder, final exam is much more difficult, they are comprehensive and covers all the materials in the course.

Homeworks and/ Late Projects

Everyone must do ample amount of problems at your own discretion to test the materials learn in the class. Some of these may appear in the exam with minor changes. Points will be deducted on late project.

WEEK	TOPICS	CHAPTERS & Appendices
1-2	Background and Course Overview S3BOARD, Nexys and Nexys2 Spartan 3, 3E boards Software Installation Introductory Xilinx Webpack, ModelSim and Silos 2001	Xilinx ISE, ModelSIM & SILOS III Boards user manuals
3	Introductory Modeling with VERILOG HDL Hardware Encapsulation Structural Description Module, ports Testbench	chap1
4-5	Logic Synthesis, Behavioral & Structural Modeling Combinational and FSM Tristates Coding Technique Latches, Flip-flops and Registers Modeling Techniques Counter Coding Technique	chap2, 3
6	Current Processes Waits, Events and control statements Producer-Consumer Handshake Module Hierarchy Instantiation, Generate-endgenerate block	chap4 chap5
7-8	Logic Level Modeling Gates and Nets Primitives Logic Gates	chap6
9	******** Midterm Exam ********
10-12	User-Defined Primitives Combinational primitives Sequential primitives Level sensitive primitives Edge-sensitive primitives	chap9
13-15	Switch Level Modeling Modeling MOS transistors Definition and using Strength levels	chap10
16	***** Final Exam ****