EE-614

EE-614 Large Scale Integrated Design

Online Synchronous (LIVE) sessions will be available for download.

Contact Email:

andresho@capitol-college.edu

Course Description:

http://www.capitol-college.edu/academicprograms/MSE1381_276.SHTML"

Textbook & References:

[ required ] Basics of CMOS Cell Design (with software on CD) by Etienne Sicard & Sonia Delmas Bendhia, Tata McGraw-Hill Publishing Company Limited, New Delhi
[ recommended ] Chip Design for Submicron VLSI: CMOS Layout and Simulation by John P. Uyemura, Thomson
[ recommended ] CMOS Circuit Design, Layout, and Simulation (revised 2nd edition) by R. Jacob Baker, Wiley-Interscience, John Wiley & Sons, Inc. Publication
[ recommended ] CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition, by Neil H.E. Weste & David Harris Pearson Eucation, Inc. Addison Wesley
[ recommended ] VLSI Cousework
[ recommended ] Nor Example in Microwind

Order online from:

http://direct.mbsbooks.com/capitol.htm

http://www.abebooks.com

Enter Author = "Etienne Sicard"
Title = "Basic of CMOS Cell Design"

FREE download WinSpice Programs

Course Grade Breakdown:

Homework (40% = "any" four out of seven). --- (due in session 4, 7, 10 & 13)
Project (30% = "any" two out of 5). --- (due in session 6 & 15)
In-class Midterm : 15% - (held in session 9)
In-class Final : 15% - (held in session 16)

Practices: NO WEIGHT

Project Report:

Project e-Report must adhere to style guide practice at the college. Click the hypertext for detail.

Grades Policy on Incomplete Work:

All works must be completed by the end of semester. In an exceptional case only will an incomplete will be issued, in such case we will follow the rules set forth on the year 2003-2004 or later publication of the College Catalog on Incomplte Grades. Please click the hypertext for detail.

Session Topics: (Style of delivery: standard lecture & live real-time demonstration)

SESSION	TOPICS	REFER TO
1	EE-614 - Syllabus IC General Trends Device Scale Down Frequency Improvement Layers, Density Design Trends WinSpice DSCH & MICROWIND	chap1
2	MOS Devices and Technology Properties of Silicon N-type and P-type Silicon Silicon Dioxide Metal Materials The MOS Switch The MOS Aspect The MOS Layout Dyanamic MOS Behaviour The Perfect Switch Layout Considerations CMOS Process	chap2
3-4	The MOS Modelling Introduction MOS Model 1 MOS Model 3 The BSIM4 MOS Model Specific MOS Devices Process Variations	chap3
5-6	The Inverter Logic Symbol CMOS Inverter Inverter Layout Inverter Simulation Power Consumption Static Characteristics Random Simulation The Inverter as a Library Cell 3-State Inverter All nMOS Inverters Ring Oscillator Latch-up Effect	chap4
7-8	Interconnections Metal Layers Contact and Vias Design Rules Capacitance Associated with Interconnections Resistance Associated with Interconnections Signal Transport Improved Signal Transport Repeaters for Improved Signal Transport Crosstalk Effects in Interconnections Antenna Effect Inductance	chap5
9	In-class MIDTERM EXAM
10	Basic Gates Combinational Logic CMOS Logic Gate Concept The NAND Gate The AND Gate The NOR Gate The OR Gate The XOR Gate Complex Gate Multiplexor Shifters Description of Basic Gates in Verilog	chap6
11-12	Arithmetics Data Formats The Adder Circuit Adder Cell Design Ripple-carry Adder Signed Adder Fast Adder Circuits Substractor Circuit Comparator Circuit Multiplier	chap7
13-14	Sequential Cell Design The Elementary Latch RS Latch D Latch Edge-triggered D Register Clock Divider Synchronous Counters Shift Registers A 24-hour Clock	chap8
15	Analog Cells Resistor Capacitor The MOS Device for Analog Design Diode-connected MOS The MOS Trasnconductance Sing Stage Amplifier Simple Differential Amplifier Wide Range Amplifier On-chip Voltage Regulator Noise	chap9
16	In-class Final Exam

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