| @CC | Title | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| click | Spartan 3 & Nexys FPGA boards --- TOOLS -- What is an FPGA? | ||||||||
| click | click | (Smart BUY) Nexys 2 the upgrade of Nexys Board | |||||||
| click | click1, click2 - part | Design overview for 4-bit Johnson ring counter | |||||||
| click | (click1 - part 1), (click2 - part 2), testing | Compiling and testing the 4-bit Johnson counter | |||||||
| Simplified Excel Code for "BASYS2" UCF --Highly recommended | |||||||||
| Simplified Excel Code for "Nexys2" UCF (500K gates ver 2.2) | |||||||||
| Simplified Excel Code for "Nexys2" UCF | |||||||||
| Simplified Excel Code for "Nexys" UCF | |||||||||
| Simplified Excel Code for "S3BOARD" UCF | |||||||||
| click | (click1 - part 1) (click2 - part 2) | Using StateCAD and StateBench for Sequence 101 detector (PDF) | |||||||
| click | (click - part) | Using ModelSim to simulate result created by StateCAD and StateBench (PDF) | |||||||
| click | (click - part ) | Simulation in ModelSim w/ user custom test Bencher | |||||||
| 3-bit counter, Z=1 if count value is 3. Uses Library Components. (PDF) | |||||||||
| Standard Component Designation. (Designation-PDF) | |||||||||
| click | click - (part 1 - part 2) | Create JK out of a D flip flop with Debounce Button as Clock (PDF) --(PDF - on S3BOARD) |
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| click | (click - part) | Mechanical Push Button Debouncer (PDF) | |||||||
| click | A light controlled by two switches (... using SILOS III in Step3.) | ||||||||
| click | Johnson 8-bit Ring Counter, Implemented on Digilent BASYS2 FPGA board
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| click | Proper Installation Procedure for SILOS Verilog simulator program (It works for 32 or 64-bit upto and including the current Windows 7 OS). | ||||||||